1. Field of the Invention
The present disclosure relates to HK/MG process flows for P-type semiconductor devices, and, more particularly, to HK/MG process flows using channel silicon germanium for work function tuning for various types of PMOS devices.
2. Description of the Related Art
The majority of present-day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETS), also called metal oxide semiconductor field effect transistors (MOSFETS) or simply MOS transistors. Typically, present-day integrated circuits are implemented by millions of MOS transistors which are formed on a chip having a given surface area.
In MOS transistors, a current flow through a channel formed between the source and drain of a MOS transistor is controlled via a gate which is typically disposed over the channel, independent from whether a PMOS transistor or an NMOS transistor is considered. For controlling a MOS transistor, a voltage is applied to the gate electrode of the gate and, when the applied voltage is greater than a threshold voltage, a current flow through the channel is induced. The threshold voltage, therefore, represents the switching characteristic of a MOS transistor and the performance of a MOS transistor depends crucially on how accurate the threshold voltage can be implemented. Adjusting the threshold voltage to a specific value during fabrication of a transistor represents a highly sophisticated task because the threshold voltage depends in a nontrivial manner on various properties of a transistor, such as size, material, etc. It is easy to see that further tuning and adjustment is necessary during fabrication processes to define threshold voltages at specific threshold levels in dependence on the specific application in which the transistor is to be employed. However, any process sequence employed in the fabrication of a MOS transistor should avoid inducing undesired variations in the threshold voltage.
Generally, current technologies providing more compact and functional electronic devices require semiconductor devices with exactly adjusted threshold voltages at different threshold voltage levels. Therefore, devices with different device types, also called flavors, are considered, such as, for example, low threshold voltage (LVT) devices, regular threshold voltage (RVT) devices, high threshold voltage (HVT) devices, and super high threshold voltage (SHVT) devices. Herein, the threshold voltage level of HVT devices is greater than the threshold voltage of RVT devices by about 80 mV. SHVT devices even show a delta in the threshold voltage level relative to RVT devices in the range of about 140-160 mV. Conventionally, complex IC structures may have a great number of LVT devices, RVT devices, HVT devices and SHVT devices, whereas the threshold voltages of one type of device should not show unacceptable variations relative to a desired value. Accordingly, efforts are directed to tune, adjust or even compensate for differences in the threshold voltage and to minimize unwanted variations during fabrication.
Conventionally, some measures for tuning the threshold voltage involve performing implantation processes which are adapted for each semiconductor device type individually for appropriately setting the required threshold voltage to a desired value. For example, halo implantation processes are conventionally performed for adjusting the threshold voltage when fabricating modern semiconductor devices, such as MOS transistors, with short channels, e.g., less than 50 nm channel length. Herein, the accordingly formed halo regions encompass source and drain extension regions of each transistor towards the channel. Basically, halo regions are regions doped with dopants of similar conductivity type as those that are present in the surrounding active region, therefore representing counter-doped regions with regard to the source and drain doping. However, the dopant concentration in halo regions is higher as compared to the surrounding active regions. At present, halo regions represent conventional measures employed for reducing so-called short channel effects which appear at small gate lengths scales and short channel lengths scales, respectively. It is apparent that, with devices of various device types or flavors possibly being formed in different regions across a single semiconductor wafer, individual tuning in each region becomes necessary in order to minimize unwanted variations. The result is a complex process flow, even posing the risk of introducing unacceptably high variations of the threshold voltage across the wafer due to the inclusion of new processes, as will be more apparent from the discussion below.
As described above, the threshold voltage depends on many different factors, of which a transistor's work function represents an important characteristic. In PMOS devices, for example, tuning of the work function involves forming a thin channel of silicon germanium material over the channel region of a transistor. The channel of silicon germanium material, often referred to as silicon germanium channel (cSiGe), is conventionally disposed between the channel region located within the semiconductor substrate and the gate electrode formed over the semiconductor substrate. Typically, cSiGe has a thickness in a range from about 80-100 Å. It is important to note that the thickness of the cSiGe has significant impact on the threshold voltage of respective PMOS transistors and any variation of the cSiGe induces a variation in the threshold voltage.
It is, thus, evident that controlling the threshold voltage of a MOS transistor is an intricate task, which becomes more complicated when applied to different types of MOS transistor devices with different levels of threshold voltages.
A further complication arises when considering the following: According to conventional process flows, each device is exposed to various implantation sequences, such as halo implantation processes, as described above. However, each device type needs to be exposed to a different implantation process for appropriately setting the threshold voltage for each single device type so as to implement various different levels of threshold voltages in dependence on the required flavor or type. That is, a variety of different implant processes are required, wherein each implantation process involves its dedicated mask pattern for reliably doping dedicated device regions and thereby tuning the threshold voltage to a desired level. As the required implantation dosages are used to compensate for unwanted differences in the threshold voltage, depending on the device type, conventionally, increased halo implantation dosages are used in the case of HVT and SHVT devices. On the other hand, high implantation dosages raise the problem of performance degradation, which is unacceptable, especially for advanced semiconductor devices. For example, an increased number of implantation sequences involves an increased number of additional masking and removal sequences, which introduce further risks of shifting the threshold voltage in an uncontrolled manner.
The above outlined problematic will be illustrated with regard to FIG. 1 which schematically illustrates how the performance of HVT and SHVT type semiconductor devices is degraded relative to RVT and LVT devices. A reason for this is seen in the extremely high halo implant doses for HVT and SHVT devices as compared to RVT and LVT devices. Masking patterns that are exposed to high implantation doses show greater resistance when subjected to mask removing processes than masking patterns that are exposed to implantation processes with moderate or low implantation doses. That is, removal of accordingly exposed masking patterns may leave masking residues and, therefore, affect subsequent processing or may damage formed structures.
The graphical representation of FIG. 1 depicts a relation between the drain current in the on-state of the device (IDS plotted on the ordinate) and the drain current in the off-state of the device (IOFF plotted on the abscissa) which is often referred to as the universal curve and which was obtained by the inventors. Herein, measurement points are indicated by triangles. A region indicated by reference SHVT in FIG. 1 denotes measurements performed with SHVT sample devices. A region indicated by reference HVT in FIG. 1 denotes measurements performed with HVT sample devices. A region indicated by reference RVT in FIG. 1 denotes measurements performed with RVT sample devices. A region indicated by reference LVT in FIG. 1 denotes measurements performed with LVT sample devices. As shown in FIG. 1, the drain current in the on-state decreases when comparing the LVT, RVT, HVT and SHVT regions. Particularly, the SHVT and HVT regions show a lower drain current in the on-state as compared to RVT and LVT regions.
In view of the above description it is desirable to provide improved HK/MG process flows for PMOS semiconductor device structures and PMOS device structures such that at least some of the aforementioned degrading effects are reduced, if not avoided.